As is known in the art, power devices of the IGBT type (“Insulated Gate Bipolar Transistor”) are used in circuits requiring high voltage and current with a moderate switching frequency, such as motor control circuitry or the like.
The performance of an IGBT device combines the advantages of a bipolar transistor (high conductivity) and those of a field-effect MOS transistor (control voltage with high input resistance), wherein MOS transistor drives the base current of the bipolar transistor.
These IGBT devices can be generally manufactured in two versions: a first one called “planar gate” and another one called “trench-gate”, whose cross-section can be seen in FIG. 1.
The structure of a “trench-gate” IGBT device includes a substrate 1 of a p+ type semiconductor material whereon an epitaxial layer is grown, split into buffer layer 2 and drift layer 3, of the n+ and n− type respectively. Two differently-doped p regions are formed on drift layer 3: a body region 4 and a deep body region 5. The n type source region 6 is integrated in the body region 5. Although FIG. 1 relates to an IGBT device, a Power MOS device could be illustrated by removing substrate layer 1.
The trench-gate structure is provided by a trench in the silicon filled in with a polysilicon layer to form gate region 7, which is separated from the other portions of the IGBT by a silicon oxide coating 8 grown on the trench walls. A deposit of dielectric 9 and a metal contact 10 complete the device, as is shown in FIG. 1.
Regions 1 and 3 are the conduction electrodes of the bipolar transistor, while the MOS transistor includes source 6, drift layer 3, and polysilicon gate 7.
The main advantages of a trench-gate device manufactured with planar technology are: the J-FET resistance is removed, with a subsequent decrease in conduction losses; and the possibility of considerably increasing the device integration scale, with a subsequent increase in current density.
On the other hand, the structure has some drawbacks. The trench lower portion causes a thickening of the electric field, with a subsequent worsening, for the same drift-layer thickness, of the device break-down voltage. A solution to this problem is providing the trench lower portion with a U-profile. This considerably improves the device break-down voltage. Also, the trench upper edge causes the formation of a beak during the gate oxide growth, which can be seen in FIG. 1 in the ring 12 and in a TEM image of the same region as is shown in FIG. 2. This unevenness causes a thickening of the electric field, due to the peak effect, with a subsequent worsening of the gate oxide break-down voltage.
A first prior art solution to solve the problem used a recessed polysilicon structure (etchback of the polysilicon protruding from the trench). In this way, the edge at the trench upper end is cut out from the device active part.
This is shown in detail in FIG. 5, wherein a comparison with FIG. 1 clearly shows the effect of the polysilicon etchback even under the trench edge level, resulting in a concave surface 14.
Another solution is to round the trench upper edge, as is shown in FIG. 3, to avoid the formation of the oxide beak during the growth thereof. This solution, however, is technically more complex.
Moreover, the structure of a “trench-gate” IGBT device has additional drawbacks. The roughness of the trench vertical walls due to silicon etching causes damage of the carrier surface mobility, as well as a worsening of the gate oxide quality. In this case accurate cleaning processes and the growth of a sacrificial oxide on trench walls before forming the gate oxide, and the following removal thereof, improve both the surface mobility and the gate oxide quality. For the same device active area, a considerable increase of the gate oxide area occurs, even in areas wherein the channel is not formed (see the gate oxide portion 11 in FIG. 4). This involves an increase in the stray capacitance linked to the device gate terminal. This problem can be avoided by providing a thick oxide layer on the trench bottom. This solution improves both the device break-down (the oxide serves as a field-ring) and the gate oxide break-down, since the wall portion, wherein a variation of the silicon crystallographic orientation occurs, is excluded from the thin oxide area, and the stray capacitance linked to the gate terminal.
The structure resulting from these possible improvements is shown in FIG. 5 wherein region 13 is filled in with thick-oxide (gate oxide+deposited dielectric).
Although providing certain advantages, the solution discussed above involves considerable complexity due to trench filling with LTO, polysilicon etchback with controlled overetch, and other steps.
What is desired, therefore, is a manufacturing method for an insulated gate semiconductor power device with an improved trench-gate structure, that overcomes the drawbacks of the prior art methods discussed above.